As process technologies for integrated circuits continue to improve, leading to smaller devices, faults in the integrated circuit which result from manufacturing defects have become more of a concern. For example, speed-related defects have become a more significant problem in integrated circuits having transistors with gate widths of 90 nm or smaller. A resistive via defect or a resistive bridge defect between two neighboring metal lines may cause a transition delay fault. A transition delay fault refers to a gate or a path that fails to meet timing requirements due to a manufacturing defect. In contrast, a “stuck-at” fault refers to a gate or path which is shorted to a certain voltage potential. Unlike a “stuck-at” fault which may be detected by the appropriate application of vectors and the observation of outputs, transition delay faults have an added requirement of an at-speed test, where test signals are applied at the operating speed of the device. That is, the transition delay fault testing is a variation of the “stuck-at” fault testing in which there is an additional restriction of speed. As the operating speeds of the devices under test continue to increase, the speeds of high speed signals used in at-speed testing have also increased.
Transition delay fault testing aims to identify faults related to slow-to-rise and slow-to-fall transitions of signals. One possible cause for a slow-to-rise or a slow-to-fall transition is a resistive bridge fault that slows down the transition time of a transistor gate, although the correct value is eventually produced. While transition delay faults are assumed to be relatively large and localized to a single site, a test of the path delay is performed under the assumption that the delays are small and distributed across a circuit or chip. A test for the path delay will test the cumulative delay across an entire path, and usually of critical paths. The problem with a path-delay test is that identifying the paths is not easy, and usually results in only a small number of paths. However, a transition delay fault model will test many paths in a net-list. Further, at-speed types of faults such as transition delay faults are usually not detected with conventional low speed tests. In addition, many such transition delay faults become future “reliability” failures. That is, a device that starts out with a marginal or timing related defect may turn into a hard failure in the field. Therefore, testing for speed-related defects such as transition delay faults has become increasingly important.
One method of catching speed-related defects is to run the conventional tests at high speed. However, the application of at-speed tests to integrated circuits has a number of practical problems. The test hardware used to test the integrated circuit has to reliably apply and sample the vectors at a very high speed, thereby increasing the cost of the tester compared to a conventional low speed tester. Further, the high-speed application of vectors also results in high current consumption, often causing the device under test to heat up. However, it is not very practical to employ sophisticated heat sinks in the test environment.
While the problems associated with at-speed testing are well recognized by industry, the solutions for at-speed testing have many deficiencies. Manufacturers of application specific integrated circuits (ASICs) have employed several approaches to at-speed testing. For example, built-in self-test (BIST) circuitry that internally applies the vectors and compresses the outputs has been used. While the interface between the tester and device will be slow, the device will be tested at very high speed. However, BIST circuitry tends to be difficult to implement, while also requiring additional silicon area of the integrated circuit. Further, testing using a BIST approach is not deterministic. That is, BIST techniques involve applying pseudo-random test vectors which do not target specific faults.
Another conventional approach uses Automated Test Pattern Generation (ATPG) and “scan test” circuits to deliver a series of closely spaced pulses to test for transition delay faults. While functional simulations may be used to verify the operation of a design, it is difficult and time consuming to produce enough simulations to provide high fault coverage. A circuit undergoing a scan test goes through an at-speed transition by use of launch and capture cells, as is well known in the art. The use of scan test circuits, as will be described in more detail below in reference to FIG. 5, simplifies test-pattern generation by reducing the design, or sections of a design, into purely combinational logic. Fast and efficient algorithms in ATPG tools developed for combinational logic may be used to generate high-fault-coverage vectors. While closely spaced pulses are used in a scan test to create the at-speed test environment, the average power consumption is kept low because closely spaced pulses are sparse. However, intellectual property (IP) cores of programmable logic devices are commonly tested using industry-standard “stuck-at” ATPG vectors applied using scan test circuits.
Accordingly, there is a need for an improved circuit for and a method of testing for faults in a programmable logic device.